Open AccessPerformance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration
Author(s) -
Tayal Shubham,
Nandi Ashutosh
Publication year - 2018
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2017.0702
Subject(s) - mosfet , static random access memory , transistor , materials science , optoelectronics , high κ dielectric , electronic engineering , stack (abstract data type) , scaling , electrical engineering , dielectric , physics , computer science , mathematics , voltage , engineering , geometry , programming language
In this work, the investigation of high‐ K gate‐stack‐based junctionless (JL) double‐gate (DG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is carried out to study the high‐ K gate dielectric effect on six‐transistor (6T)‐static random‐access memory (SRAM) built with JLDG‐MOSFET. It is observed that the utilisation of the high‐ K gate dielectric in JLDG‐MOSFETs improves the static noise margin (SNM) that is the stability of the cell as well as access time (AT) which reflects the delay performance of the SRAM cell. Furthermore, scaling down of L g degrades the stability. Moreover, it is also described that the enhancement in hold SNM (ΔHSNM = HSNM ( K =40) −HSNM ( K =3.9) ), read SNM (ΔRSNM = RSNM ( K =40) −RSNM ( K =3.9) ), and write SNM (ΔWSNM = WSNM ( K =40) −WSNM ( K =3.9) ) is restricted at lower L g without much enhancement in the improvement of read AT and write AT. Therefore, it is appropriate to consider higher channel length (∼30 nm) while designing high‐ K gate‐stacked‐based JLDG‐MOSFETs for the 6T‐SRAM cell.