Open AccessEvaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual‐ k spacer FinFETs
Author(s) -
Gopal Maisagalla,
Sharma Vishal,
Vishvakarma Santosh K.
Publication year - 2017
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2017.0318
Subject(s) - static random access memory , materials science , noise margin , optoelectronics , transistor , silicon germanium , electronic engineering , mosfet , noise (video) , silicon , electrical engineering , voltage , computer science , engineering , artificial intelligence , image (mathematics)
This work aims to investigate the device performance of silicon–germanium (SiGe)/Si carbide (SiC) source/drain (S/D) asymmetric dual‐ k spacer underlap Fin‐field‐effect transistor (SiGe/SiC‐AsymD‐ k FinFET) with Si channel for high performance and robust SRAM cell. Strain‐induced mobility enhancement due to the Si 1− x Ge x /Si 1− y C y S/D leads to a significant drive current enhancement of the proposed device. The introduced asymmetric dual‐ k spacer at source side offers excellent gate control over the channel. By exploiting asymmetry in current, the authors prove that it is possible to achieve mitigation of read–write conflict in 6T SRAM bit cell. SiGe/SiC‐AsymD‐ k FinFET SRAM offers 8.39% improvement in hold static noise margin, 14.28% in read and 18.06% in write mode over conventional FinFET‐based 6T SRAM bit cell. When compared to conventional FinFET 6T SRAM bit cell, the proposed 6T SRAM bit cell shows lesser temperature sensitivity of cell stability.