Open AccessAnalysis of trap‐assisted tunnelling in asymmetrical underlap 3D‐cylindrical GAA‐TFET based on hetero‐spacer engineering for improved device reliability
Author(s) -
Beohar Ankur,
Yadav Nandakishor,
Vishvakarma Santosh Kumar
Publication year - 2017
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2017.0311
Subject(s) - quantum tunnelling , trap (plumbing) , reliability (semiconductor) , materials science , optoelectronics , physics , nanotechnology , quantum mechanics , power (physics) , meteorology
A unique design for an asymmetrical underlap (AU) cylindrical‐gate‐all‐around (GAA)‐ n‐ tunnel field effect transistor (TFET) based on hetero‐spacer engineering with trap‐assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as I ON , I OFF , SS, I ON /I OFF, C gs , and C gd have been investigated, while included TAT model and compared the examined device with AU GAA‐TFET based on homo‐spacer (HS) dielectric. On the basis of observation, the proposed device increases ON current as high as 2.1 × 10 −6 A/µm, which corresponds to 1024 times improvement in I ON /I OFF when compared with device based on HS. It also suppresses ambipolar behaviour with fast switching ON–OFF transition due to low leakage current ( I OFF ). These performances are mainly produced due to AU and low‐ k spacer dielectric which is replaced by high‐ k dielectric over source side spacer of the device, whereas drain side spacer is placed with high‐ k material along with increase in series resistance across drain–channel junction caused by drain underlap. Low‐ k spacer reduces the fringing field, and the depletion does not form at the source–gate edge, hence high source–channel tunnelling junction.