Open AccessJunction‐less charge plasma TFET with dual drain work functionality for suppressing ambipolar nature and improving radio‐frequency performance
Author(s) -
Tirkey Sukeshni,
Raad Bhagwan Ram,
Gedam Anju,
Sharma Dheeraj
Publication year - 2018
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2017.0197
Subject(s) - ambipolar diffusion , tunnel field effect transistor , optoelectronics , electrical engineering , work function , materials science , transistor , capacitance , parasitic capacitance , electronic circuit , drain induced barrier lowering , nand gate , logic gate , inverter , electrode , electronic engineering , plasma , field effect transistor , engineering , nanotechnology , physics , voltage , quantum mechanics , layer (electronics)
This work deals with a distinct concept to realise the junction‐less tunnel field effect transistor (JL TFET) by creating the plasma of charges. The crux of this study is to reduce ambipolar conduction and to improve high‐frequency figure of merits. To construct a JL TFET, initially P + silicon film is considered and then metal electrodes are used to form drain and channel region. The drain electrode is separated into two sections and the work function of section adjacent to channel is selected higher than the other section. This provides a non‐uniform doping profile in the drain region creating large barrier at the drain/channel junction to prevent the ambipolar conduction. Ambipolarity is reduced to 1 × 10 − 14from 1 × 10 − 8at V gs = − 1.5 V . The selection of work function and length of drain electrode adjunct to channel is crucial for optimising device performance. This optimisation provides information that work function >4.0 eV and length = 10 nm completely suppresses the ambipolarity which is around 1 × 10 − 21with little degradation in ON‐current. The high work function for the section of drain electrode adjunct to channel provides lower gate‐to‐drain capacitance ( ∼ 2.67 fF ) and superior high‐frequency responses. Furthermore, performance assessment at circuit level is done by implementing primary digital circuits as inverter and NAND logic with lookup table based Verilog‐A model.