Open AccessMulti‐valued logic design methodology with double negative differential resistance transistors
Author(s) -
Ji Yuchao,
Chang Sheng,
Wang Hao,
Huang Qijun,
He Jin,
Yi Fan
Publication year - 2017
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2017.0163
Subject(s) - logic family , logic optimization , logic gate , pass transistor logic , computer science , logic synthesis , adder , resistor–transistor logic , differential (mechanical device) , electronic engineering , electronic circuit , sequential logic , binary number , arithmetic , mathematics , algorithm , digital electronics , electrical engineering , engineering , cmos , aerospace engineering
Multi‐valued logic (MVL) is one of the promising alternatives of binary logic since it has a high‐logic density, which brings a vision of simpler circuit structure. Based on a novel concept as double negative differential resistance field effect transistor and its analytic description, a design methodology utilising the mechanism of monostable‐to‐multistable transition logic element (MMLE) for MVL is proposed in this study. The basic ternary logic gates are designed as a complete logic set, and a compact ternary four‐input full adder is constructed as an example of function circuits. Comparing with binary circuit and ternary circuit based on conventional design, the circuit shows advantage in device cost and other properties. The results verify that this MMLE design methodology has a good information load ability, which will have a brilliant prospect in MVL circuits.