Open AccessRS flip‐flop implementation based on all spin logic devices
Author(s) -
Wang Sen,
Cai Li,
Feng Chaowen,
Cui Huanqing,
Yang Xiaokuo,
Zhao Hongyan
Publication year - 2017
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2016.0589
Subject(s) - sequential logic , flip flop , computer science , scalability , logic gate , cmos , pass transistor logic , electronic circuit , electronic engineering , logic block , logic family , bistability , logic synthesis , field programmable gate array , algorithm , digital electronics , electrical engineering , computer hardware , physics , engineering , optoelectronics , database
All spin logic (ASL) device is one of the promising post‐CMOS candidates. Owing to unique features such as non‐volatility, simple configuration, ultra‐low‐switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non‐volatility and bistable states of ASL device, an RS flip‐flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin‐transport/magneto‐dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip‐flop will be an useful component for designing large‐scale ASL sequential logic circuits.