Open AccessUltra‐low leakage SRAM design with sub‐32 nm tunnel FETs for low standby power applications
Author(s) -
Makosiej Adam,
Gupta Navneet,
Vakul Naga,
Vladimirescu Andrei,
Cotofana Sorin,
Mahapatra Santanu,
Amara Amara,
Anghel Costin
Publication year - 2016
Publication title -
micro and nano letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.25
H-Index - 31
ISSN - 1750-0443
DOI - 10.1049/mnl.2016.0442
Subject(s) - static random access memory , standby power , quantum tunnelling , leakage (economics) , subthreshold slope , electrical engineering , transistor , optoelectronics , ultra low power , computer science , subthreshold conduction , materials science , tunnel field effect transistor , leakage power , power (physics) , mosfet , embedded system , electronic engineering , physics , field effect transistor , engineering , voltage , power consumption , quantum mechanics , economics , macroeconomics
Tunnel‐field‐effect transistors (TFETs) operate by quantum band‐to‐band tunnelling and display a steeper subthreshold slope than MOSFETs which substantially diminishes the standby current. This work explores the TFET‐based SRAM utilisation for Low STandby Power applications. An 8 T TFET SRAM cell operating at V DD = 1 V, which, in contrast to other 6 T TFET SRAMs, is write‐disturb‐ and half‐selection‐free is proposed. Simulations based on 30 nm p‐ and n‐TFETs models relying on I D , C GS , C GD vs. V GS , and V DS look‐up tables extracted from TCAD, indicate that the proposed cell has a Read SNM and a Write SNM of 120 and 200 mV, respectively, which are well above state of the art values repotted in the literature. When utilised in an 128 × 128‐bit memory array the proposed cell enables read and write operation at 3.84 GHz and 806 MHz, respectively, and a cell leakage of less than 2fA/bit, which makes it an excellent choice for Internet of Things applications.