Open AccessDesign and implementation of parallel CRC algorithm for fibre channel on FPGA
Author(s) -
Chuxiong Wu,
Haifeng Shi
Publication year - 2019
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2019.0727
Subject(s) - cyclic redundancy check , computer science , field programmable gate array , redundancy (engineering) , process (computing) , data transmission , algorithm , computer hardware , parallel computing , embedded system , decoding methods , operating system
Fibre channel (FC) provides the high‐speed and low‐latency communication between the end systems, widely used in data storage, aerospace applications and large electronic equipment including radar systems. Excellent in error detection and easy to be implemented in hardware, cyclic redundancy check (CRC) is an important error detection method widely used in network data transmission. This study introduces a design and development of parallel CRC algorithm for the hardware implementation on FPGA to meet the specifications for FC. The algorithm can process 128‐bit parallel data in a block by broken it into four 32‐bit data and calculate their CRC, respectively, based on the linear feedback shift register, simplifying the calculation process and reducing resource consumption.