Open AccessFPGA‐based fault injection design for 16K‐point FFT processor
Author(s) -
Mao ChuangAn,
Xie Yu,
Wei Xin,
Xie YiZhuang,
Chen He
Publication year - 2019
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2019.0703
Subject(s) - field programmable gate array , fault injection , computer science , embedded system , soft error , static random access memory , reliability (semiconductor) , fault (geology) , fast fourier transform , fault coverage , computer hardware , electronic circuit , electronic engineering , engineering , electrical engineering , algorithm , power (physics) , software , physics , quantum mechanics , seismology , programming language , geology
There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits. Aiming at reliability evaluation of very‐large‐scale integration circuits implemented in SRAM‐based field programmable gate arrays, a fault injection platform is constructed based on the soft error mitigation controller in this study. The authors adopt a 16K‐point fast Fourier transformation processor as the design under test (DUT) and inject errors into different positions. The effectiveness of this platform is varied by comparing the results of DUT with Golden data. Compared with the traditional reliability testing techniques, the fault injection method proposed in this study has the advantages of low cost, short test period and low resource consumption. Hence, the proposed fault injection design is suitable for circuits consuming huge resources and large number of repeating tests.