Open AccessImplementation architecture of signal processing in pulse Doppler radar system based on FPGA
Author(s) -
Yang Ming,
Yang Jing,
Hou Yanan,
Jin Cheng
Publication year - 2019
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2019.0644
Subject(s) - field programmable gate array , computer science , digital signal processing , pulse compression , radar , computer hardware , signal (programming language) , architecture , embedded system , signal processing , digital signal processor , pulse (music) , constant false alarm rate , electronic engineering , real time computing , engineering , telecommunications , algorithm , art , detector , visual arts , programming language
A kind of high speed and parallel hardware architecture is proposed and designed for digital signal processing of high frequency Pulse Doppler radar here. The platform is based on one XC7K410T FPGA, two XC7K325T FPGAs, one TMS320C6678 DSP, and four sets of MT41J256M8 DDR3. The details of implementation including pulse compression, moving target detection and constant‐false‐alarm rate are described. The simulation results and resource consumption are presented to demonstrate the advantages of the proposed FPGA implementation architecture.