Design for the system of high‐speed data transmission and data pre‐processing for synthetic aperture radar imaging based on the system‐on‐a‐programmable‐chip

For the chirp scaling algorithm of synthetic aperture radar imaging, an efficient transmission of a large volume of data is indispensable. Prior to imaging, there is a requirement for appropriate pre‐processing of the echo signal by digital down conversion (DDC). The DDC module has to remove the carrier, having an appropriate filtering processing and down‐sampling processing. No matter what imaging mode is chosen, such as the stripmap mode, spotlight mode, and sliding spotlight, the needs of the whole imaging system are matched by setting a series of configurations about this pre‐processing module and this transmission module. The system‐on‐a‐programmable‐chip constituted by the Advanced RISC Machine and field programmable gate array (FPGA) is the perfect experimental platform to test the performance of this system. Some of the algorithms, which are more feasible for this specific project for pre‐processing in Maltab, were transplanted to FPGA using the VHSIC Hardware Description Language for functional verification. Finally, the processing results in Matlab were compared with this system to find the difference. At the same time, the time that elapsed from the 2 GB original data entering the system to the time the processed results were completely returned to the PC was also counted.