Open AccessParallel wideband digital up‐conversion architecture with efficiency
Author(s) -
Liu Tao,
Tian Shulin,
Guo Lianping
Publication year - 2019
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2018.9061
Subject(s) - computer science , baseband , bandwidth (computing) , cascaded integrator–comb filter , bottleneck , electronic engineering , filter (signal processing) , digital filter , mixing (physics) , signal processing , signal (programming language) , interpolation (computer graphics) , wideband , computer hardware , root raised cosine filter , digital signal processing , embedded system , engineering , telecommunications , frame (networking) , physics , programming language , quantum mechanics , computer vision
Owing to the limited processing speed of current digital signal processing devices, digital generated signal frequency and bandwidth based on digital up‐conversion technique has long been a bottleneck. Interpolation on the baseband signal puts great pressure on the following filtering and mixing operation. In this study, an efficient parallel architecture is presented, which moves the interpolation behind the filtering and mixing, and adopts parallel numerically controlled oscillator (NCO) arrays and poly‐phase low‐pass filter arrays to achieve the anticipated orthogonal mixing signal and prototype filter. Parallel NCO decomposition principle and mathematical derivation are elaborated, and realisation of the poly‐phase filter arrays is also discussed. The proposed post‐interpolation architecture can effectively relieve the filtering and mixing pressure including operation rate and computational complexity, which will benefit the hardware implementation. In the end, verification test of signal up‐conversion with 400 MHz bandwidth is launched to certify the architecture validity.