Open AccessModified capacitor voltage balancing sorting algorithm for modular multilevel converter
Author(s) -
Zhang Jie,
Liu Jun,
Liu Jiayu,
Fang Wanliang,
Hou Junxian,
Dong Yifeng
Publication year - 2019
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2018.8910
Subject(s) - sorting , capacitor , modular design , computer science , voltage , sorting algorithm , computation , harmonic , electronic engineering , power (physics) , control theory (sociology) , topology (electrical circuits) , electrical engineering , algorithm , engineering , physics , operating system , control (management) , quantum mechanics , artificial intelligence
The modular multilevel converter (MMC) with large‐scale sub‐modules has the advantage of simpler modulation, lower switching frequency, and lower harmonic component, thus would be very promising in voltage source converter (VSC)–high voltage direct current transmission systems. Conventional capacitor voltage balancing algorithm suffers from insufficient grouping and sorting techniques. Therefore, it might result in excessive computation and high switching frequency of power electronic devices. To address the problem, a modified capacitor voltage balancing sorting algorithm is proposed in this paper. The proposed algorithm could avoid sorting all the module capacitor voltages by selecting only a certain number of the largest or smallest module capacitor voltages, and thus reduces time complexity greatly without losing control precision. Furthermore, the proposed algorithm focuses on the sub‐modules whose capacitor voltage exceeds the limits, while the switching states of the other sub‐modules are maintained to some degrees by employing the maintaining factor. Therefore, the switching frequency of the power electronic devices is further reduced. The performance of the proposed algorithm is evaluated through a time‐domain MMC–HVDC simulation in PSCAD/EMTDC. Results show that the proposed algorithm is able to balance the module voltage with lower computation and reduce the switching frequency of power devices significantly, without noticeably increasing the capacitor voltage ripples.