FPGA implementation of impedance‐compensated phase‐locked loop for HVDC converters

The phase‐locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance‐compensated phase‐locked loop (IC‐PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the phase locking more robust against transients and harmonics. The IC‐PLL has an improved dynamic response as compared with the traditional approaches. However, earlier studies on the IC‐PLL are mainly based on off‐line simulations. In this study, an actual IC‐PLL is constructed in hardware and its performance is investigated by connecting it to a real‐time model of a line‐commutated converter‐based HVDC system on a real‐time digital simulator. The proposed IC‐PLL is constructed using a field‐programmable gate array platform. Paralleled and pipelined structures are implemented on the FPGA to achieve low latency and high speed. The performance of the IC‐PLL is tested by exposing it to different type of system disturbances such as sudden step change in power, voltage magnitude change and voltage distortion. Results are compared with the traditional trans‐vector PLL. The results show the performance of the IC‐PLL is superior.