Open AccessAllocating resources based on a model of coarse‐grained reconfigurable architecture
Author(s) -
Zhang Huizhen,
Pan Yubiao,
Zhang Yiwen,
Wang Cheng
Publication year - 2019
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2018.5230
Subject(s) - field programmable gate array , computer science , reconfigurable computing , computer architecture , resource (disambiguation) , graph , key (lock) , architecture , set (abstract data type) , embedded system , distributed computing , parallel computing , theoretical computer science , computer network , programming language , art , computer security , visual arts
Reconfigurable resource utilisation is a key factor that impacts the performance of reconfigurable instruction set processors (RISPs), which can customise their instruction set for special applications. In this study, the authors propose a novel method to improve reconfigurable resource utilisation of RISPs based on field programmable gate array (FPGA) chips. The method provides a graph multi‐colouring allocating algorithm based on a simplified reconfigurable resource model. In the model, they construct three kinds of FPGA‐based coarse‐grained reconfigurable resources and abstract their attributes mainly through their location and area. The authors’ algorithm employs a graph multi‐colouring method to allocate the coarse‐grained reconfigurable resources to custom instructions for RISPs. Experimental results demonstrate that their model and algorithm reinforce a state‐of‐the‐art resource utilisation method for RISPs, and reveals some interesting regularities which provide creditable new insights of reconfigurable resource utilisation.