Open AccessCMV reduction for five‐level ANPC converter by PS‐PWM strategy
Author(s) -
Liu Feipeng,
Xu Lie,
Wang Kui,
Zhou Peiyi,
Li Yongdong
Publication year - 2018
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2018.0020
Subject(s) - pulse width modulation , reduction (mathematics) , voltage , modulation (music) , voltage reduction , capacitor , topology (electrical circuits) , common mode signal , computer science , control theory (sociology) , network topology , engineering , electronic engineering , materials science , electrical engineering , physics , mathematics , artificial intelligence , control (management) , acoustics , computer network , geometry , digital signal processing , analog signal
Five‐level active neutral point clamped (ANPC) converter has become one of the most attractive topologies in industry applications, especially in the field of the motor drive. A novel common‐mode voltage (CMV) reduction strategy for five‐level ANPC is presented, which is based on the phase‐shifted pulse‐width modulation (PS‐PWM). A basic PS‐PWM method is presented, which can realise the NP voltage and the flying capacitor (FC) voltages balance. Moreover, a general CMV reduction method is summarised. The proposed CMV reduction strategy can minimise the CMV by injecting zero‐sequence voltage to the modulation wave and it does not affect the ability of NP voltage and FC voltages balance. The validity of the proposed CMV reduction method based on PS‐PWM strategy is verified by simulation.