Open AccessParticle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis
Author(s) -
Sengupta Anirban,
Kachave Deepak
Publication year - 2017
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2016.0378
Subject(s) - overhead (engineering) , particle swarm optimization , computer science , datapath , modular design , transient (computer programming) , reduction (mathematics) , fault tolerance , fault (geology) , distributed computing , embedded system , algorithm , mathematics , geometry , seismology , geology , operating system
Owing to aggressive shrinking in nanometre scale as well as faster devices, particle strike manifesting itself into transient fault spanning multiple cycle and multiple units will be the centre‐focus of application specific datapath generated through high‐level synthesis (HLS)/architectural synthesis. Addressing each problem above separately leads to large area/delay overhead; thus tackling both problems concurrently, leads to huge incurred overhead. To tackle this complex problem, this paper proposes a novel low cost particle swarm optimisation driven dual modular redundant (DMR) based HLS methodology for generation of a transient fault secured design secured against its temporal and spatial effects. The authors' approach provides a low cost optimised fault secured solution through a particle swarm optimisation exploration framework based on user area‐delay constraints. Results indicated that proposed approach obtains an area overhead reduction of 34.08% and latency overhead reduction of 5.8% compared with a recent approach.