Open AccessParallel‐in encoding of quasi‐cyclic low‐density parity‐check codes
Author(s) -
Zhang Peng,
Du Shuai,
Liu Changyin,
Jiang Qianqian
Publication year - 2016
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2016.0122
Subject(s) - encoder , accumulator (cryptography) , low density parity check code , computer science , shift register , electronic circuit , parallel computing , adder , arithmetic , encoding (memory) , parity (physics) , parity bit , algorithm , mathematics , decoding methods , physics , electrical engineering , telecommunications , latency (audio) , engineering , artificial intelligence , particle physics , operating system
Serial‐in encoders for quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes are widely used. To provide flexible interfaces and reduce complexity, three parallel‐in QC‐LDPC encoders are proposed. One consists of shift‐register–adder–accumulator (SRAA) circuits, the others consist of rotate‐left‐accumulator (RLA) circuits. It is shown that a partially parallel‐in encoder is comparable to or even superior to a serial‐in one based on the same circuits; an RLA‐based encoder is preferable to a SRAA‐based one with the same speed, whether they are partially parallel‐in or fully parallel‐in.