Open Access23 µW 8.9‐effective number of bit 1.1 MS/s successive approximation register analog‐to‐digital converter with an energy‐efficient digital‐to‐analog converter switching scheme
Author(s) -
Sun Lei,
Ko Chi Tung,
Ho Marco,
Ng Wai Tung,
Leung Ka Nang,
Choy Chiu Sing,
Pun Kong Pang
Publication year - 2014
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2014.0137
Subject(s) - capacitor , effective number of bits , successive approximation adc , electronic engineering , figure of merit , energy (signal processing) , computer science , electrical engineering , cmos , physics , engineering , voltage , quantum mechanics , computer vision
This study presents a successive approximation register analog‐to‐digital converter with an energy‐efficient switching scheme. A split‐most significant bit capacitor array is used with a least significant bit‐down switching scheme. Compared with the conventional binary‐weighted capacitor array, it reduces the area and average switching energy by 50 and 87% under the same unit capacitor. Moreover, capacitor matching requirement is relaxed by 75%. A prototype design was fabricated in a 0.13 µm complementary metal oxide semiconductor process. It consumes 23.2 µW under 1 V analog supply and 0.5 V digital supply. Measured results show a peak signal‐to‐distortion‐and‐noise ratio of 55.2 dB and an effective resolution bandwidth up to 1.1 MHz when it operates at 1.1 MS/s. Its figure‐of‐merit is 44.1 fJ / conversion‐step.