Open AccessDevice and circuit performance analysis of double gate junctionless transistors at L g = 18 nm
Author(s) -
Sahu Chitrakant,
Singh Jawar
Publication year - 2014
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2013.0269
Subject(s) - inverter , cmos , optoelectronics , transistor , static random access memory , electrical engineering , materials science , subthreshold conduction , mosfet , electronic engineering , voltage , engineering
The design and characteristics of double‐gate (DG) junctionless (JL) devices are compared with the DG inversion‐mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso‐ V th for both n‐ and p‐type of devices. The JL device shows lower drain‐induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG) logic, inverter circuit and static random access memory (SRAM) stability analysis using JL devices, rather than a complementary metal‐oxide semiconductor (CMOS) configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device‐circuit methodology in ATLAS technology aided computer design (TCAD) mixed‐mode simulator.