Open AccessImproved dual sided doped memristor: modelling and applications
Author(s) -
Shrivastava Anup,
Khalid Muhammad,
Singh Komal,
Singh Jawar
Publication year - 2014
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2013.0265
Subject(s) - memristor , memistor , noise margin , spice , computer science , electronic engineering , cmos , logic gate , materials science , electrical engineering , voltage , resistive random access memory , engineering , transistor
Memristor as a novel and emerging electronic device having vast range of applications suffer from poor frequency response and saturation length. In this paper, the authors present a novel and an innovative device structure for the memristor with two active layers and its non‐linear ionic drift model for an improved frequency response and saturation length. The authors investigated and compared the I–V characteristics for the proposed model with the conventional memristors and found better results in each case (different window functions) for the proposed dual sided doped memristor. For circuit level simulation, they developed a SPICE model of the proposed memristor and designed some logic gates based on hybrid complementary metal oxide semiconductor memristive logic (memristor ratioed logic). The proposed memristor yields improved results in terms of noise margin, delay time and dynamic hazards than that of the conventional memristors (single active layer memristors).