Open AccessCapacitive digital‐to‐analogue converters with least significant bit down in differential successive approximation register ADCs
Author(s) -
Sun Lei,
Pun KongPang,
Ng WaiTung
Publication year - 2014
Publication title -
the journal of engineering
Language(s) - English
Resource type - Journals
ISSN - 2051-3305
DOI - 10.1049/joe.2013.0219
Subject(s) - converters , register (sociolinguistics) , bit (key) , capacitive sensing , computer science , arithmetic , 12 bit , 8 bit , electronic engineering , electrical engineering , computer hardware , mathematics , engineering , voltage , cmos , philosophy , linguistics , computer security
This Letter proposes a least significant bit‐down switching scheme in the capacitive digital‐to‐analogue converters (CDACs) of successive approximation register analog‐to‐digital converter (ADC). Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V cm ‐based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL)/integral non linearity (INL) performance.