Capacitive digital‐to‐analogue converters with least significant bit down in differential successive approximation register ADCs | Zendy

Sun Lei | Zendy; Pun KongPang | Zendy; Ng WaiTung | Zendy

Open Access

Capacitive digital‐to‐analogue converters with least significant bit down in differential successive approximation register ADCs

Author(s) -

Sun Lei,

Pun KongPang,

Ng WaiTung

Publication year - 2014

Publication title -

the journal of engineering

Language(s) - English

Resource type - Journals

ISSN - 2051-3305

DOI - 10.1049/joe.2013.0219

Subject(s) - converters , linearity , differential nonlinearity , successive approximation adc , capacitor , switched capacitor , electronic engineering , integral nonlinearity , chip , capacitive sensing , cmos , 8 bit , electronic circuit , shaping , computer science , energy (signal processing) , mathematics , electrical engineering , engineering , voltage , telecommunications , statistics

This Letter proposes a least significant bit‐down switching scheme in the capacitive digital‐to‐analogue converters (CDACs) of successive approximation register analog‐to‐digital converter (ADC). Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V cm ‐based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL)/integral non linearity (INL) performance.

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