Wireless network‐on‐chip: a survey

To alleviate the complex communication problems arising in the network‐on‐chip (NoC) architectures as the number of on‐chip components increases, several novel interconnect infrastructures have been recently proposed to replace the traditional on‐chip interconnection systems that are reaching their limits in terms of performance, power and area constraints. Wireless NoC (WiNoC) is among the most promising scalable interconnection architectures for future generation NoCs. In this study, the authors first provide a general description of the WiNoC architecture. Then, they discuss the research problems under five categories: topology, routing, flow control, antenna and reliability. Open research issues for the realisation of the WiNoC are also discussed.