Open AccessNovel low‐latency, high‐resolution and low‐cost time synchronisation
Author(s) -
Aghdaei Ali,
Reza Zekavat Seyed A.
Publication year - 2017
Publication title -
iet wireless sensor systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.433
H-Index - 27
eISSN - 2043-6394
pISSN - 2043-6386
DOI - 10.1049/iet-wss.2017.0025
Subject(s) - oversampling , latency (audio) , computer science , field programmable gate array , low latency (capital markets) , real time computing , bandwidth (computing) , multiplier (economics) , accumulator (cryptography) , decimation , electronic engineering , computer hardware , algorithm , engineering , telecommunications , computer network , economics , macroeconomics
This study presents an oversampling‐based low‐latency, high‐resolution and low‐cost timing synchronisation technique for digital receivers. Traditional timing synchronisation employs matched filter to estimate the signal coarse time of arrival. Here, latency increases through oversampling and resolution improves via higher bandwidth. The proposed method uses single bit quantisation to employ XNOR blocks instead of multiplier and accumulator blocks in the traditional method. This substantially decreases complexity incorporating less field‐programmable gate array (FPGA) surface area.