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Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures
Author(s) -
Poczekajło Paweł,
Wawryn Krzysztof
Publication year - 2018
Publication title -
iet signal processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.384
H-Index - 42
eISSN - 1751-9683
pISSN - 1751-9675
DOI - 10.1049/iet-spr.2017.0450
Subject(s) - field programmable gate array , finite impulse response , algorithm , computer science , transfer function , gate array , digital filter , impulse (physics) , rotation (mathematics) , filter (signal processing) , adder , computer hardware , latency (audio) , artificial intelligence , engineering , telecommunications , electrical engineering , computer vision , physics , quantum mechanics
A novel algorithm for the realisation of an orthogonal digital system performing three‐dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state‐space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field‐programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct‐form structure consisting of adders, multipliers, and delay elements.

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