Open AccessCORDIC‐based window implementation to minimise area and pipeline depth
Author(s) -
Aggarwal Supriya,
Khare Kavita
Publication year - 2013
Publication title -
iet signal processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.384
H-Index - 42
eISSN - 1751-9683
pISSN - 1751-9675
DOI - 10.1049/iet-spr.2012.0021
Subject(s) - cordic , pipeline (software) , computer science , window (computing) , parallel computing , rotation (mathematics) , series (stratigraphy) , window function , algorithm , field programmable gate array , computer hardware , filter (signal processing) , artificial intelligence , paleontology , computer vision , biology , programming language , operating system
Filtering is one of the most important modules in signal processing paradigm. This study presents a field‐programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area‐delay product. First, the authors modify the Taylor series approximation order used in the scaling‐free CORDIC, to completely eliminate the scale‐factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro‐rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift‐add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.