Open AccessGraphical modelling of pinched hysteresis loops of memristors
Author(s) -
Wang XiaoMeng,
Hui ShuYuen Ron
Publication year - 2017
Publication title -
iet science, measurement and technology
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.418
H-Index - 49
eISSN - 1751-8830
pISSN - 1751-8822
DOI - 10.1049/iet-smt.2016.0210
Subject(s) - memristor , hysteresis , loop (graph theory) , control theory (sociology) , excitation , computer science , topology (electrical circuits) , electronic engineering , physics , mathematics , engineering , electrical engineering , condensed matter physics , artificial intelligence , control (management) , combinatorics
In this study, a graphical modelling approach of the pinched hysteresis loops exhibited by memristors is presented. This method provides a tool to emulate the hysteresis loop pinched at the origin, with the lobe area varying with the excitation frequency. The direction of the pinched hysteresis loop can be controlled. This graphical modelling method provides an alternative to describe the behaviour of memristors without deriving the coupled non‐linear differential equations typically required for physical memristors. The method has been successfully applied to model the Hewlett–Packard memristor device.