Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

This study presents energy and area‐efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform – field programmable gate arrays (FPGAs). An area‐efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio‐temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier‐less reconfigurable architectures and a design strategy is devised for its implementation.