Open AccessEfficient architecture and hardware implementation of coherent integration processor for digital video broadcast‐based passive bistatic radar
Author(s) -
Shan Tao,
Liu Shengheng,
Zhang Yimin D.,
Amin Moeness G.,
Tao Ran,
Feng Yuan
Publication year - 2016
Publication title -
iet radar, sonar and navigation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.489
H-Index - 82
eISSN - 1751-8792
pISSN - 1751-8784
DOI - 10.1049/iet-rsn.2015.0006
Subject(s) - computer science , chirp , bistatic radar , computer hardware , electronic engineering , radar , real time computing , embedded system , radar imaging , engineering , telecommunications , laser , physics , optics
In this study, the problem of efficient implementation of a coherent integration processor in passive bistatic radars (PBRs) in the presence of range migration is addressed. The authors present a coherent integration architecture for PBR, which consists of a frequency‐domain pulse compression module to reduce the overall runtime for the computation of the cross‐ambiguity function, and an efficient decimated keystone transform module based on the chirp z ‐transform to compensate the range migration. The proposed architecture is then implemented in a hybrid central processing unit plus graphic processing unit scheme. Real measurement data are used to verify the superior integration performance and reduced computational complexity achieved by the proposed scheme.