Open AccessTo study unplanned islanding transient response of microgrid by implementing MSOG and SRF‐PLL based hierarchical control in the presence of non‐linear loads
Author(s) -
Norozpour Niazi Ahmad,
Vasegh Nastran,
Motie Birjandi Ali Akbar
Publication year - 2020
Publication title -
iet renewable power generation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.005
H-Index - 76
eISSN - 1752-1424
pISSN - 1752-1416
DOI - 10.1049/iet-rpg.2019.0506
Subject(s) - control theory (sociology) , islanding , microgrid , phase locked loop , ac power , harmonic , grid connection , electrical impedance , robustness (evolution) , voltage source , output impedance , engineering , integrator , computer science , voltage , electronic engineering , distributed generation , physics , control (management) , biochemistry , chemistry , quantum mechanics , artificial intelligence , renewable energy , jitter , electrical engineering , gene
This study considers the hierarchical control of microgrid and harmonic compensation of non‐linear load specially in transition from grid‐connected to unplanned islanding. The proposed controllers are based on the stationary reference frame with hierarchical control levels (inner, primary, and secondary). In the inner control loop, proportional and multi‐resonant voltage and current controllers for three‐phase voltage source inverters are proposed. Moreover, a droop control is used to share active and reactive power in the primary control loop. To achieve decoupled active and reactive power sharing, virtual impedance loop is implemented, too. The mentioned procedure increases the total impedance and consequently reduces the initial current and subsequently facilitates the continuous connection of DGs to the MG. To attain smoother transition, selective harmonic virtual impedance is applied by multiple second‐order generalised integrator module to extract the fundamental positive sequence and harmonic components of the output current of the DGs. In secondary control level, synchronisation procedure is considered to make connection and restoration by the advanced three‐phase synchronous reference frame PLL with in‐loop moving average filter which significantly enhances its disturbance rejection capability. The results are shown smoother transition, robustness, and high performance of the proposed hierarchical control VSIs during variation of system configuration.