Open AccessZero DC voltage ride through of a hybrid modular multilevel converter in HVDC systems
Author(s) -
Lu Maozeng,
Hu Jiabing,
Lin Lei,
Xu Kecheng
Publication year - 2017
Publication title -
iet renewable power generation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.005
H-Index - 76
ISSN - 1752-1424
DOI - 10.1049/iet-rpg.2016.0108
Subject(s) - voltage , converters , modular design , capacitor , high voltage direct current , redundancy (engineering) , engineering , electrical engineering , electronic engineering , control theory (sociology) , computer science , direct current , control (management) , reliability engineering , artificial intelligence , operating system
This study presents a comprehensive analysis and a suppression method of sub‐modules’ (SMs’) voltage stress in the hybrid modular multilevel converters when riding through zero DC voltage faults in high‐voltage direct‐current (HVDC) systems. First, the general DC fault ride through (FRT) strategy considering the redundancy of the arm voltage generation scheme under a reduced dc‐link voltage is derived. Then full‐bridge sub‐modules (FBSMs’) voltage stress for the conventional DC‐FRT schemes with and without common‐mode voltage injection are analysed. Finally, on the basis of the available full‐bridge SM capacitor energy control strategy, an improved method implemented by energy interaction between half‐bridge sub‐modules and FBSMs is presented. The proposed DC‐FRT scheme can make all SM capacitor voltages balanced at their rated values during the zero DC voltage conditions. Simulated results are provided to demonstrate the validity of the analytical results and the feasibility of the proposed DC‐FRT scheme.