Open AccessAnalysis and implementation of a generalised switched‐capacitor multi‐level inverter having the lower total standing voltage
Author(s) -
Majumdar Saikat,
Mahato Bidyut,
Jana Kartick Chandra
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2020.0458
Subject(s) - capacitor , inverter , voltage , switched capacitor , voltage drop , topology (electrical circuits) , electrical engineering , computer science , electronic engineering , engineering
Most of the switched capacitor multi‐level inverters (SC‐MLIs) are designed with a single isolated voltage source and capacitors where voltage levels are obtained by the addition of these sources only. The common problems arise in SC‐MLIs are an unequal number of conducting paths, higher voltage drop across capacitors, sum of total inverter DC link voltages across the highest voltage rated switches and higher total standing voltage (TSV). The motivation of this work is to design a hybrid generalized SC‐MLI with reduced components aiming to maintain a constant voltage across the capacitors, to achieve higher voltage gain with minimum components used, minimum conducting paths, lower TSV, cost‐effective and an efficient inverter. A generalised SC‐MLI structure is also proposed, which can multiply the voltage across the capacitors in a binary asymmetrical manner. The design parameters of the proposed hybrid SC‐MLI topology are compared with the recently developed SC‐MLIs in terms of the number of switches, capacitors, TSV, conducting switches and industrial components cost to prove its superiority and effectiveness of the proposed inverter. The experimental prototype of a specimen 9‐level and 17‐level inverters are implemented using DS1103 and the corresponding results are presented.