Open AccessResilient multilevel inverter topology with improved reliability
Author(s) -
Chappa Anilkumar,
Gupta Shubhrata,
Sahu Lalit Kumar,
Gupta Krishna Kumar
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2020.0158
Subject(s) - topology (electrical circuits) , network topology , robustness (evolution) , capacitor , reliability (semiconductor) , inverter , computer science , voltage , engineering , power (physics) , electronic engineering , electrical engineering , physics , computer network , biochemistry , chemistry , quantum mechanics , gene
Reliability is one of the significant worries of multilevel inverter (MLI) owing to the higher number of capacitors and switches. In this regard, fault‐tolerant single‐phase MLI topology with improved reliability is proposed in this work. Apart from the reduced device count, the proposed topology has fault‐tolerant characteristics without any extra switches or legs. Moreover, the voltage of the capacitor is balanced under pre and post‐fault operation without any external circuit. Less number of the turn‐on devices and power losses promise higher reliability of the proposed topology in comparison with recently proposed topologies. The reliability of the proposed topology, as well as recently proposed topologies, has been evaluated. A detailed quantitative comparison of the proposed inverter topology has been carried out with the recent literature. The robustness and effectiveness of the proposed topology are carried out under various operating conditions in the SIMULINK environment. Finally, an experimental test bench of the proposed topology is built and the obtained experimental results validate the simulation results.