Open AccessMulti‐mode fault‐tolerant control strategy for cascaded H‐bridge multilevel inverters
Author(s) -
Wang Tianzhen,
Zhang Jiahui,
Wang Han,
Wang Yide,
Diallo Demba,
Benbouzid Mohamed
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2020.0109
Subject(s) - h bridge , insulated gate bipolar transistor , inverter , fault tolerance , waveform , control theory (sociology) , voltage , fault (geology) , total harmonic distortion , computer science , harmonic , topology (electrical circuits) , electronic engineering , engineering , control (management) , electrical engineering , physics , distributed computing , quantum mechanics , artificial intelligence , seismology , geology
This study proposes a multi‐mode fault‐tolerant control (FTC) strategy, for cascaded H‐bridge multilevel inverters, to provide the most suitable fault tolerance scheme for different single or double arbitrary insulated gate bipolar transistor (IGBT) faults. Firstly, all faulty modes are classified into three fault clusters according to the number and location of faulty IGBTs. Then, the matching mechanism of the multi‐mode FTC strategy corresponding to the three clusters is described, and the appropriate FTC algorithm is selected for each cluster. In particular, a new FTC method has been proposed for Cluster I that includes double IGBT fault in different H‐bridges and different groups. This method improves the utilisation efficiency of healthy IGBTs in the faulty H‐bridges, and minimises the voltage level drop after the fault. Finally, the multi‐mode FTC strategy has been applied to a seven‐level inverter through simulation. Results have shown significant improvement of the output voltage waveform symmetry and harmonic distortion reduction for the three clusters. The new FTC method has been applied to an experimental five‐level inverter. The obtained results confirm the validity of the methodology. With the proposed strategy, the output voltage has a lower harmonic distortion and a better symmetry thanks to the attenuation of the undesirable DC component.