Open AccessAsymmetric cascade multilevel inverter with self‐balanced switched‐capacitor unit and single source
Author(s) -
Ye Yuanmao,
Lin Mingliang,
Wang Xiaolin
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2019.1098
Subject(s) - cascade , capacitor , switched capacitor , voltage , harmonics , h bridge , boosting (machine learning) , topology (electrical circuits) , computer science , inverter , voltage source , control theory (sociology) , electrical engineering , electronic engineering , engineering , control (management) , chemical engineering , machine learning , artificial intelligence
The technique of single‐source cascaded H‐bridge multilevel inverter (MLI) has been reported in previous works. In this study, a self‐balanced series/parallel switched‐capacitor (SC) is introduced to further develop this type of MLIs to generate more output levels. Each cascaded H‐bridge is fed by an SC unit. All components in each SC unit withstand the same voltage stress, but different SC units address different voltages. With this asymmetric feature, different H‐bridges are responsible for providing levels with different voltage intervals so that the cascaded MLI can generate numerous levels with a single dc source and fewer components. Compared with the conventional asymmetrical cascaded MLIs, just a single dc source is required, capacitors’ voltages are balanced automatically, high boosting ability and more output levels are achieved with SC technique in the proposed MLIs. To synthesise the output voltage as close as possible to sinusoidal shape but with less switching loss, comparative analysis of nearest level control and equal area criterion is provided to modulate the proposed MLI with 13‐level output. Experimental results demonstrate that the proposed MLI has high efficiency and low harmonics.