Open AccessFPGA‐based active disturbance rejection velocity control for a parallel DC/DC buck converter‐DC motor system
Author(s) -
Guerrero Esteban,
Guzmán Enrique,
Linares Jesús,
Martínez Alberto,
Guerrero Gerardo
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2019.0832
Subject(s) - dc motor , field programmable gate array , control theory (sociology) , robustness (evolution) , converters , active disturbance rejection control , computer science , matlab , controller (irrigation) , buck converter , pid controller , control engineering , engineering , voltage , electrical engineering , computer hardware , control (management) , physics , state observer , artificial intelligence , quantum mechanics , nonlinear system , temperature control , chemistry , biology , operating system , biochemistry , agronomy , gene
This study deals with the robust velocity controller of a DC motor driven by means of parallel DC/DC buck power converters with equal current distribution, from the perspective of a generalised proportional–integral (GPI)‐observers‐based active disturbance rejection controller (ADRC). The multivariable system is subject to constant torque load demands and changes in the internal parameters. The linear output feedback controllers actively counteract the exogenous and endogenous disturbances that result from the cascading parallel converter and the DC motor. A rapid prototyping tool is used for synthetising the proposed controller into a field‐programmable gate array (FPGA) which is based on Matlab/Simulink and a Xilinx System Generator. The robustness of the proposed ADRC system is analysed. The FPGA‐based implementation setup is presented with the purpose of validating the theoretical calculations of the proposed DC motor velocity control.