Open AccessFault tolerant architecture of an efficient five‐level multilevel inverter with overload capability characteristics
Author(s) -
Sadanala Chiranjeevi,
Pattnaik Swapnajit,
Singh Vinay Pratap
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2019.0736
Subject(s) - redundancy (engineering) , inverter , topology (electrical circuits) , capacitor , fault tolerance , network topology , computer science , power (physics) , architecture , electronic engineering , engineering , reliability engineering , electrical engineering , distributed computing , computer network , voltage , physics , quantum mechanics , art , visual arts
Multilevel inverters (MLIs) are gaining the widespread attention in various industrial applications. However, the advantages offered by MLIs are only met with the employment of a high number of semiconductor switches and capacitors, which are most vulnerable amongst all the power electronic components. Thus, designing of a reliable MLI topology is a need of the present hour. In this regard, a five‐level fault tolerant MLI topology has been proposed here. The proposed MLI topology comprises the main inverter topology and a redundant leg. The main inverter topology comprises bidirectional switches which result in high power losses under both healthy and faulty conditions. Eighteen different cases arising from the inherent redundancy available in the main inverter topology have been analysed to achieve the optimum solution for obtaining high efficiency. A novel redundant leg architecture has been designed, which achieves significantly improved efficiency under all faulty conditions. Under overload conditions, the proposed redundant leg architecture is capable of reducing the current stress on the main inverter switches. An effective qualitative and quantitative comparison of the proposed topology with the recent literature has been presented. The feasibility of the proposed concepts has been verified by the obtained simulation and hardware results.