Open AccessEvaluation of high power density achievement of optimum 4‐level capacitor‐clamped DC–DC boost converter with passive lossless snubber circuit by using Pareto‐Front method
Author(s) -
Kasiran Mohd Amirul Naim,
Ponniran Asmarashid,
Yatim Mohd Hafizie,
Itoh Junichi
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2019.0604
Subject(s) - snubber , inductor , power density , capacitor , inductance , power (physics) , materials science , lossless compression , electronic engineering , electrical engineering , engineering , computer science , voltage , physics , quantum mechanics , data compression , computer vision
This study presents the evaluation of the proposed optimum 4‐level capacitor‐clamped DC–DC boost converter (CCBC) for high power density achievement by using Pareto‐Front method. The 4‐level CCBC with considering high switching frequency can greatly reduce the inductor size and volume. High switching frequency caused the switching devices to suffer high semiconductor losses. Consequently, the cooling device volume is increased as well. Thus, this study presents soft‐switching technique in the 4‐level CCBC for semiconductor losses reduction. The combination of optimum design of inductor, improvement of circuit structure and soft‐switching technique may lead to the highest power density of the converter. A 400 W of the 4‐level CCBC converter is designed and experimentally verified. The results show that the inductance and inductor volume required in the 4‐level CCBC is reduced by 88.89 and 80.75%, respectively. Besides, Pareto‐Front curve shows the highest power density of soft‐switching technique with the proposed 4‐level CCBC is 6.51 kW/dm 3 at 800 kHz of switching frequency with efficiency of 97.20%.