Open AccessLow‐cost analogue active gate driver for SiC MOSFET to enable operation in higher parasitic environment
Author(s) -
Krishna Miryala Vamshi,
Hatua Kamalesh
Publication year - 2020
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2019.0589
Subject(s) - gate driver , mosfet , parasitic element , parasitic capacitance , electrical engineering , gate equivalent , transistor , gate oxide , nand gate , electronic engineering , materials science , capacitance , logic gate , engineering , voltage , physics , electrode , quantum mechanics
Operating silicon carbide (SiC) metal–oxide–semiconductor field‐effect transistor (MOSFET) at its rated switching speed may not be always feasible due to excessive voltage and current overshoot and ringing caused by layout parasitic inductance and load parasitic capacitance. This study proposes a low‐cost analogue active gate driver technique for switching SiC MOSFET in the presence of moderate amount of layout parasitic inductance (<200 nH) and load parasitic capacitance (<300 pF). In this study, a d i / d t based closed‐loop active gate driver circuit is implemented using low‐cost signal level transistors. The present work explains the working of the gate driver during turn‐on and turn‐off switching transients. A detailed design methodology for the gate driver is presented using its high‐frequency model. The proposed active gate driver (AGD) has been verified in hardware platform using a double pulse test setup and in a boost converter test setup. Cree make 1200 V, 36 A SiC MOSFET (C2M0080120D) is used for evaluating the proposed active gate driver. The proposed circuit has sufficient operating bandwidth to drive SiC MOSFET and it is realised with low‐cost transistors.