Open AccessReduced device count version of single‐stage switched‐capacitor module for cascaded multilevel inverters
Author(s) -
Bhatnagar Pallavee,
Agrawal Rekha,
Gupta Krishna Kumar
Publication year - 2019
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2018.6017
Subject(s) - switched capacitor , capacitor , topology (electrical circuits) , voltage , reduction (mathematics) , power (physics) , network topology , electronic engineering , computer science , decoupling capacitor , electrical engineering , engineering , physics , mathematics , geometry , quantum mechanics , operating system
Switched capacitors are being increasingly employed in multilevel inverters for various applications. Of the new topologies that have been recently introduced, single‐stage switched‐capacitor module (S 3 CM) has gained a lot of attention. In this work, a modified version of S 3 CM is presented that leads to a significant reduction in a number of power switches, with a simultaneous reduction in total peak inverse voltage. The proposed topology can generate 9 voltage levels in symmetric configuration and 11 voltage levels in asymmetric configuration with two dc sources, two capacitors, and eight power switches. Moreover, for the higher voltage‐rated power switches in the structure, the switching losses are minimised by fundamental frequency operation of these switches. The operation and the performance of the proposed topology have been validated through simulation and experimental results of a single‐phase prototype with symmetric and asymmetric source configurations.