Open AccessPLL with frequency and initial‐phase‐angle detectors: performance analysis and speed/robustness trade‐off improvement
Author(s) -
Zarei Mohammad,
Karimadini Mohammad
Publication year - 2019
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2018.6001
Subject(s) - phase locked loop , pll multibit , robustness (evolution) , control theory (sociology) , phase detector , phase frequency detector , frequency offset , electronic engineering , detector , total harmonic distortion , phase noise , harmonic analysis , offset (computer science) , low pass filter , computer science , engineering , filter (signal processing) , telecommunications , voltage , electrical engineering , channel (broadcasting) , artificial intelligence , orthogonal frequency division multiplexing , chemistry , capacitor , biochemistry , charge pump , control (management) , gene , programming language
Phase‐locked loops (PLLs) are well known tools for synchronisation and measurement of the fundamental parameters of power grid signals. Signals measured in the electrical industry may contain disturbances such as harmonic distortion, dc offset, noise and unbalanced conditions which destroy the pure sinusoidal form of signals. The present study improves the trade‐off between PLL disturbance‐rejection capability and dynamic‐response speed. An improved PLL is proposed based on frequency and initial‐phase‐angle detectors (FIPD) and moving average filter for measurement of the signal parameters in both single‐phase and three‐phase applications. The proposed PLL is called improved FIPD‐based PLL (IFIP‐PLL) and provides satisfactory disturbance rejection and response time. The proposed structure effectively decreases the estimation error. Simulation and experimental results show the superiority of IFIP‐PLL over conventional PLLs.