Open AccessSix‐phase SVPWM with common‐mode voltage suppression
Author(s) -
Zheng Jian,
Rong Fei,
Li Peiyao,
Huan Shoudao,
He Yigang
Publication year - 2018
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2018.5692
Subject(s) - voltage , pulse width modulation , control theory (sociology) , common mode signal , three phase , class (philosophy) , computer science , mode (computer interface) , electromagnetic coil , space vector , phase (matter) , topology (electrical circuits) , mathematics , engineering , physics , electrical engineering , artificial intelligence , telecommunications , control (management) , combinatorics , quantum mechanics , transmission (telecommunications) , analog signal , operating system
There are two common‐mode voltages (CMVs) in a six‐phase machine with two Y‐connected windings shifted by 30°, which bring adverse effects on the six‐phase system. In this study, a method of six‐phase space vector pulse width modulation (SVPWM) is proposed, which can suppress the magnitude and frequency of the two CMVs. First, all basic vectors are divided into 16 classes, from which two classes of basic vectors are selected. With these two classes of basic vectors, some auxiliary vectors are constructed according to an optimisation model. Then a reference vector is synthesised by using these auxiliary vectors. There are two kinds of synthesis schemes, single‐class synthesis and two‐class synthesis. Finally, optimal sequences of the basic vectors that play a role in each switching period are obtained. The experimental results show that the peak‐to‐valley value of CMV is only one‐third of the DC‐bus voltage of the converter in the two‐class synthesis, and the frequency of CMV is only three times of the line voltage fundamental frequency, which is far below the switching frequency of the converter.