Open AccessDC offset minimisation of three‐phase multilevel inverter configuration under fault and DC link voltage unbalance conditions
Author(s) -
Airineni Madhukar Rao,
Keerthipati Sivakumar
Publication year - 2018
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2017.0128
Subject(s) - inverter , transformer , voltage , photovoltaic system , three phase , electrical engineering , topology (electrical circuits) , computer science , maximum power point tracking , matlab , electronic engineering , engineering , control theory (sociology) , control (management) , artificial intelligence , operating system
In recent days, multilevel inverters are quite popular in the photovoltaic system to improve the power quality. One of the popular multilevel inverters for medium power applications is neutral point clamping inverter. However, with the limited number of switching combinations, energy balancing and fault‐tolerant operation is a major issue. The absence of energy balance mechanism may lead to unequal charge and discharge patterns in the batteries used in off‐grid applications, which in turn results in the un‐equal voltage at the batteries terminals. The difference in voltage between the sources can introduce the DC voltage offset at AC output, which causes serious problems when fed to the transformers or inductive loads like the induction motor. To address this problem, a five‐level inverter is proposed which is capable of energy balancing between the two DC sources, minimising the DC voltage offset and able to operate in some fault‐tolerant conditions. At the same time, this topology uses less number of switches as compared to conventional three‐phase five‐level inverters. The proposed topology is developed by combining conventional two‐level and three‐level inverters. The topology is verified by simulation using Matlab Simulink and tested on a laboratory prototype. The control algorithm for prototype is implemented with the help of Xilinx SPARTAN‐6 (XC6SLX9) FPGA board.