Open AccessGeneral topology for asymmetrical multilevel inverter with reduced number of switches
Author(s) -
Boora Kamaldeep,
Kumar Jagdish
Publication year - 2017
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2016.1011
Subject(s) - topology (electrical circuits) , total harmonic distortion , network topology , inverter , voltage , harmonics , matlab , computer science , commutation , control theory (sociology) , electronic engineering , engineering , electrical engineering , control (management) , artificial intelligence , operating system
The new emerging topologies in multilevel inverter field with reduced dc voltage sources and device counts, offer high power capability with less commutation losses and less harmonics in output voltage. However, these topologies have some disadvantages such as voltage balancing problem, increased number of electronic components, larger in size and complex control techniques. This study proposes a new asymmetrical multilevel inverter topology which requires less number of switching devices and driver circuits as compared to conventional multilevel inverter topologies. In the proposed topology, eight switches are required for generation of 15‐level single phase output voltage. The proposed topology is simple and can be extended easily to get more number of levels in the output voltage. Therefore, there is a significant reduction in size, cost and complexity for higher number of levels in output voltage. All positive and negative levels as well as performance parameter in term of Total Harmonic Distortion in the output voltage generated by proposed MLI have been evaluated using simulation in MATLAB environment. Various simulation and experimental results are presented to verify the operational accuracy of the proposed topology for a single phase 15‐level inverter.