Open AccessReliability improvement of transistor clamped H‐bridge‐based cascaded multilevel inverter
Author(s) -
Gautam Shivam Prakash,
Gupta Shubhrata,
Kumar Lalit
Publication year - 2017
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2016.0574
Subject(s) - reliability (semiconductor) , h bridge , transistor , inverter , bridge (graph theory) , reliability engineering , computer science , electronic engineering , electrical engineering , engineering , physics , power (physics) , voltage , medicine , quantum mechanics
Reduced voltage stress and low‐total harmonic distortion are the main causes for such widespread application of multilevel inverters (MLIs) in various industrial sectors. However, reliability is one of the major concerns of MLIs as it uses a large number of switches as compared with two‐level inverters. Therefore, a newly developed transistor clamped H‐bridge inverter is proposed in the literature which uses a relatively less number of switches and DC sources as compared with cascaded H‐bridge but lacks in reliability due to the absence of redundant states. Hence, in this study, the reliability improvement strategy for newly developed five‐level transistor clamped H‐bridge‐based cascaded inverter is proposed which can be generalised for any number of levels. In the proposed fault tolerant strategy, the fault can be broadly classified based on the two main legs of the proposed inverter. Moreover, the proposed fault tolerant strategy does not require any kind of external circuit for maintaining its capacitor voltage in the balanced state. Finally, to validate the concept, a laboratory prototype of the five‐level inverter is developed and results are obtained successfully.