Open AccessRapid and generalised space vector modulation algorithm for cascaded multilevel converter based on zero‐order voltage constraint
Author(s) -
Wang Cui,
Zhang Yun,
Tang Xiongmin,
Chen Sizhe
Publication year - 2016
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2015.0367
Subject(s) - algorithm , unit cube , voltage reference , space vector modulation , voltage , computer science , correctness , support vector machine , modulation (music) , control theory (sociology) , topology (electrical circuits) , mathematics , pulse width modulation , engineering , artificial intelligence , control (management) , discrete mathematics , combinatorics , electrical engineering , philosophy , aesthetics
To simplify space vector modulation (SVM) algorithm, reduce zero‐order voltage, and find the shortest switching path of the switching state vectors, a rapid and generalised SVM algorithm for cascaded multilevel converter is proposed. Using coordinate transformation which leads to all basic vectors locating in the integer grids in new coordinates, the algorithm simplifies the locating of basic vectors synthesising reference vectors and also their dwell time calculation. Switching state vectors calculation based on minimum zero‐order voltage criteria reduces the workload of SVM. To find a most suitable switching path, the switching state vectors are mapped in three‐dimensional (3D) space coordinates. Switching frequency is minimal along adjacent two sides of a unit cube's surface in 3D space coordinates, which improves performance of the converter. Finally, a three‐cell seven‐level converter experimental prototype is built and tested. Simulation and experimental results are consistent with the theoretical prediction, which verifies the correctness and effectiveness of the proposed algorithm.