Open AccessReduction in number of devices for symmetrical and asymmetrical multilevel inverters
Author(s) -
Gautam Shivam Prakash,
Sahu Lalit Kumar,
Gupta Shubhrata
Publication year - 2016
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2015.0176
Subject(s) - reduction (mathematics) , computer science , topology (electrical circuits) , electronic engineering , mathematics , electrical engineering , engineering , geometry
Multilevel inverter (MLI) is receiving remarkable recognition due to its reduced voltage stress across the power switches and low total harmonic distortion in output voltage. However, MLI incorporates large number of semiconductor switches and hence increases its complexity. In this study, new structures of symmetrical and asymmetrical MLI are proposed. The proposed structures offer reduced number of controlled switches, power diodes, capacitors and DC sources as compared with classical and recently proposed topologies in the line. Reduction of switch count, driver circuit and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Moreover significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topologies with the classical topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi‐carrier pulse width modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/Simulink and feasibility of topology has been validated experimentally.