Open AccessDesign of synchronous reference frame phase‐locked loop with the presence of dc offsets in the input voltage
Author(s) -
Kulkarni Abhijit,
John Vinod
Publication year - 2015
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2014.0878
Subject(s) - phase locked loop , control theory (sociology) , dc bias , reference frame , computer science , offset (computer science) , grid , transfer function , pll multibit , charge pump , interconnection , electronic engineering , voltage , frame (networking) , engineering , mathematics , electrical engineering , telecommunications , control (management) , artificial intelligence , geometry , jitter , programming language , capacitor
A novel small‐signal state‐space model is formulated for the commonly used synchronous reference frame phase‐locked loop (SRF‐PLL). Using this model, the effect of dc offsets as a function of SRF‐PLL design parameters is quantified. It is shown that the unit vectors produced by the phase‐locked loop (PLL) will have dc offsets when the input contains dc offsets. This can result in dc injection to the grid, which is highly undesirable. A systematic design method is proposed which ensures that dc injection to the grid is within the prescribed grid interconnection standards. In this design, SRF‐PLL bandwidth is analytically computed for different levels of dc offsets in the input. The proposed design is compared with conventional pre‐filter‐based designs addressing the dc offset issue. The proposed design method results in the fastest transient response for given worst‐case input dc offset without changing the PLL structure. Such a design for the SRF‐PLL is computationally less intensive and is preferable when low‐end digital controllers are used. The analytical results have been verified experimentally.