Open AccessImproved three‐phase, five‐level pulse‐width modulation switched voltage source inverter
Author(s) -
Odeh Charles I.
Publication year - 2015
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2014.0133
Subject(s) - pulse width modulation , inverter , total harmonic distortion , modulation index , topology (electrical circuits) , modulation (music) , waveform , grid tie inverter , voltage , power (physics) , control theory (sociology) , pulse frequency modulation , electronic engineering , computer science , pulse amplitude modulation , engineering , electrical engineering , physics , pulse (music) , maximum power point tracking , acoustics , control (management) , quantum mechanics , artificial intelligence
This study presents an improved three‐phase, five‐level pulse‐width modulation (PWM) switched voltage source inverter. The single‐carrier, multilevel PWM scheme is employed to generate the gating signals for the power switches. Operational principles with switching functions are given. By controlling the amplitude modulation index, three‐ and five‐level output phase voltage waveforms can be achieved. For modulation indices of 0.45, and 0.9, the proposed inverter topology was subjected to an R – L load and the respective number of output voltage level were synthesised. For a step change in the modulation index, the response of the proposed multilevel inverter circuit topology is demonstrated. Fast Fourier transform analyses of the output line voltage waveforms, at the indicated depth of modulation, were carried out and the corresponding total harmonic distortion values were obtained. Comparison of the proposed inverter configuration and the classical 3‐ϕ topologies is given based on the power circuit component count. Moreover, analysis of the conduction power losses in the power semiconductor switches of the proposed inverter topology is given. To verify the performance of the proposed inverter architecture, simulations and experiments are carried out on a 3.46 kW rated prototype of the proposed inverter for an R – L load; and adequate results are presented.