Method to improve trade‐off performance for split‐gate power U‐shape metal‐oxide semiconductor field‐effect transistor with compound trench dielectrics

A split‐gate power U‐shape metal‐oxide semiconductor field‐effect transistor (MOSFET) with compound trench dielectrics (CTDSG UMOSFET) is proposed. The dielectric layer of CTDSG UMOS is divided into two layers, employing different K values dielectrics for each one. A new electric field peak is generated in drift region. So, a higher breakdown voltage (BV) for devices and a higher doping in the drift region, lower specific on‐resistance ( R SP ) can be realised. This work provides theoretical and simulation analyses of CTDSG UMOS device. Compared to split‐gate RESURF stepped oxide (SG RSO) UMOS, the BV 2 /R SP of CTDSG UMOS with w = 0.8 μm, L = 6.0 μm and t OX = 0.5 μm is increased by 73% when relative permittivity ε 1 = 7.5, 92% when ε 1 = 9 and 100% when ε 1 = 12. R SP decreases with the increasing of relative permittivity ε 1 adopted, when ε 1 is less than a certain value.